Verification EngineerID:44588

45,000 PHP ~ 75,000 PHPMakatiOver 3 months ago

Overview

  • Salary

    45,000 PHP ~ 75,000 PHP

  • Industry

    Manufacturing

  • Job Description

    Job Description (Main role)：
    ・ Extraction and creation of verification items
    ・ Construction of verification environment (Verilog, VHDL, SystemVerilog, UVM)
    ・ Execution of verification using simulators
    ・ Document creation
    ・ Clarification of required specifications
    ・ Circuit design using Hardware design language (Verilog-HDL, VHDL)

Qualifications

  • Requirement

    ＜MUST＞
    ・Knowledge of digital circuits (Hardware design language, fundamentals of digital circuits, etc.)
    ・Verification of digital circuits using simulator (Verilog or VHDL)
    -can travel overseas (mid- to long-term depending on the project)

    ＜BETTER＞
    ・Design of digital circuits using Hardware design language (Verilog or VHDL)

  • English Level

    Business

  • Other Language

    English

Additional Information

  • Benefit

    SSS
    PHILHEALTH
    PAGIBIG
    13month pay
    Assigned or travel to JAPAN, CHINA

    Other details will inform during interview or Offer

  • Working Hour

    8:00 ~ 17:00

  • Holiday

    Satudays
    Sundays
    philippne holiday

  • Job Function