Verification EngineerID:44588
45,000 PHP ~ 75,000 PHPMakati3个月以上前概述
薪资
45,000 PHP ~ 75,000 PHP
产业类别
Manufacturing
工作内容
Job Description (Main role):
・ Extraction and creation of verification items
・ Construction of verification environment (Verilog, VHDL, SystemVerilog, UVM)
・ Execution of verification using simulators
・ Document creation
・ Clarification of required specifications
・ Circuit design using Hardware design language (Verilog-HDL, VHDL)
资格
应征条件
<MUST>
・Knowledge of digital circuits (Hardware design language, fundamentals of digital circuits, etc.)
・Verification of digital circuits using simulator (Verilog or VHDL)
-can travel overseas (mid- to long-term depending on the project)
<BETTER>
・Design of digital circuits using Hardware design language (Verilog or VHDL)英文
Business
其他语言
English
附加信息
福利制度
SSS
PHILHEALTH
PAGIBIG
13month pay
Assigned or travel to JAPAN, CHINA
Other details will inform during interview or Offer工作时间
8:00 ~ 17:00
假日
Satudays
Sundays
philippne holiday职业类别