Digital Design EngineerID:44772
50,000 PHP ~ 80,000 PHPOrtigas, Pasig2ヶ月 前概要
給与
50,000 PHP ~ 80,000 PHP
業界
Engineering
仕事内容
• Study datasheet, user specifications, and other input specifications
• Create Verification list (block or top-level) based on the specified requirements
• Design digital circuits with good consideration on power, area, and testability
• Write RTL and perform verification to check that it confirms with the expected
behavior
• Attend and present during design reviews attended by the project team members
and review panel
• Communicate with backend, test and other division groups until mass production
of product
• Write documentations and share technical know-how
求めている人材
応募条件
• BS or MS in Electronics/Computer/Electrical Engineering major in Microelectronics
• At least 5 years of proven/in-depth experience in Digital Design
(FPGA, CPLD, ASIC)
• Experience in creating digital specifications, RTL implementation and completion
of all required reports for sign-off
• Expert in Verilog. Knowledge in SystemVerilog is an advantage
• In depth experience on the following:
Industry standard tools (Cadence/Synopsis/Mentor Graphics) for lint check, clock
domain crossing check, equivalence check, and RTL simulations.
• Scripting like Perl, Shell, Tcl, Python is preferred
• Knowledge in STA, clock-tree synthesis, DFT, fault-analysis, product development
cycle (planning, development, sample validation)
• Excellent problem solving and analytical skills
• A team player and able to collaborate with multi-site design centers
• Above average oral and written communication skills. Japanese Language skills is
an advantage but not a requirement英語
Business
その他言語
English
その他
福利厚生
TBD
就業時間
8am ~ 5:00pm
休日
Flexible time schedule from 7am-10am
職種
ログインして下さい。