资格

• 应征条件

  • BS or MS in Electronics/Computer/Electrical Engineering major in Microelectronics
  • At least 5 years of proven/in-depth experience in Digital Design
  (FPGA, CPLD, ASIC)
  • Experience in creating digital specifications, RTL implementation and completion
  of all required reports for sign-off
  • Expert in Verilog. Knowledge in SystemVerilog is an advantage
  • In depth experience on the following:
  Industry standard tools (Cadence/Synopsis/Mentor Graphics) for lint check, clock
  domain crossing check, equivalence check, and RTL simulations.
  • Scripting like Perl, Shell, Tcl, Python is preferred
  • Knowledge in STA, clock-tree synthesis, DFT, fault-analysis, product development
  cycle (planning, development, sample validation)
  • Excellent problem solving and analytical skills
  • A team player and able to collaborate with multi-site design centers
  • Above average oral and written communication skills. Japanese Language skills is
  an advantage but not a requirement

• 英文

  Business

• 其他语言

  English