Verification EngineerID:44588

45,000 PHP ~ 75,000 PHPMakati3ヶ月以上前

概要

  • 給与

    45,000 PHP ~ 75,000 PHP

  • 業界

    Manufacturing

  • 仕事内容

    Job Description (Main role)：
    ・ Extraction and creation of verification items
    ・ Construction of verification environment (Verilog, VHDL, SystemVerilog, UVM)
    ・ Execution of verification using simulators
    ・ Document creation
    ・ Clarification of required specifications
    ・ Circuit design using Hardware design language (Verilog-HDL, VHDL)

求めている人材

  • 応募条件

    ＜MUST＞
    ・Knowledge of digital circuits (Hardware design language, fundamentals of digital circuits, etc.)
    ・Verification of digital circuits using simulator (Verilog or VHDL)
    -can travel overseas (mid- to long-term depending on the project)

    ＜BETTER＞
    ・Design of digital circuits using Hardware design language (Verilog or VHDL)

  • 英語

    Business

  • その他言語

    English

その他

  • 福利厚生

    SSS
    PHILHEALTH
    PAGIBIG
    13month pay
    Assigned or travel to JAPAN, CHINA

    Other details will inform during interview or Offer

  • 就業時間

    8:00 ~ 17:00

  • 休日

    Satudays
    Sundays
    philippne holiday

  • 職種